7.6. Absent and vestigial hardware (reference-base leftovers)¶
The SM6350 is a smartphone SoC; the shipped device tree and overlays are derived
from the Qualcomm lagoon reference design and instantiate whole subsystems
this e-reader does not populate. This page catalogues those blocks with the
static evidence that they are unwired: a block being in the tree does not
mean it exists on the board. This is the same pattern as the
XBL AMOLED panel string (Boot image: kernel, DTB, ramdisk, config) and the mmWave/5G RF thermal
zones (ADSP and CDSP firmware); this page collects the SoC-fabric cases.
7.6.1. Camera / Titan ISP — present, unpopulated¶
The full Titan camera pipeline is instantiated in the base tree:
ISP / compute blocks:
qcom,cam-cpas(CPAS bus/QoS),qcom,cam-isp,qcom,cam-ipe,qcom,cam-bps,qcom,cam-icp,qcom,cam-jpeg,qcom,cam-lrme,qcom,cam-cdm-intfandqcom,cam-req-mgr.Sensor interfaces: two CCI controllers (
qcom,cci×2) and four CSI PHYs (qcom,csiphy-v1.2.3,csiphy0–csiphy3).Clock / power: CAMCC (
qcom,lagoon-camccat0xAD00000, Clock tree — GCC, domain CCs, RPMh), theTITAN_SS/TITAN_CAM_CCwindows in the XBL MMAP, and the PM8008 I²C camera PMIC (qcom,i2c-pmicat USID 8, Pin control — TLMM and the PMIC GPIOs).Pins: four
CCI_I2Cgroups (gpio2/3, 39/40, 41/42, 43/44) and fiveCAM_MCLK0–4clocks (gpio29–33) in the TLMM (Pin control — TLMM and the PMIC GPIOs).Overlay wiring: the
dtbooverlays even declare four camera modules —qcom,cam-sensor@2/4/5/6with matchingqcom,eeprom@*andqcom,actuator@4/5/6— a full rear+front reference camera set.
Despite all of that, the Note Air5 C ships no camera. The tree and overlay are the SM6350 reference camera design carried through unchanged; the CCI/MCLK pads and the PM8008 rail are declared but unused. (Verifying that the pads are truly unconnected is a board-inspection question, not a static one, but nothing in the boot chain or the product touches the camera path.)
7.6.2. PCIe — absent¶
There is no PCIe controller in the tree: zero qcom,pcie / pcie@ /
device_type = "pci" nodes. The only trace is a single apps-SMMU translation
unit stub, pcie_tbu@1519d000 (Base kernel device tree (the SoC boot contract)) — a leftover SMMU TBU
with no root complex behind it. XBL confirms it: in uefiplat.cfg the
## PCIE ## section has #PCIeRPNumber=0x0101 commented out, so no root
ports are enabled. PCIe is not present on this device.
7.6.3. HDMI — vestigial audio/bridge stubs¶
No HDMI connector exists, but the reference tree leaves HDMI stubs:
three
qcom,msm-dai-q6-hdmiaudio DAIs (the Q6 AFE HDMI-audio front ends, ADSP and CDSP firmware), andqcom,msm-hdmi-dba-codec-rx— an HDMI “display-bridge-adapter” codec node.
These are audio/bridge plumbing for an HDMI output the device does not have.
7.6.4. DisplayPort — present SoC block, not the display path¶
qcom,dp_display@ae90000 (sde_dp) is a real MDSS DisplayPort controller —
part of the SoC, capable of DP-alt-mode over USB-C. It is not the device’s
display path: the panel is e-ink driven through the DPU and the EPD FPGA
(Display pipeline — DSI transport to the color e-ink TCON, Pin control — TLMM and the PMIC GPIOs). Whether DP-alt-mode is exposed on the
Type-C port is a board-populate question; the primary and boot-time display is
e-ink, and nothing below userspace drives DP.
7.6.5. Where the other leftovers live¶
For completeness, the vestigial items documented elsewhere:
XBL AMOLED panel naming and reference splash — Boot image: kernel, DTB, ramdisk, config.
mmWave/5G RF thermal zones, RF-card hwids, VoWiFi/ePDG config on the ADSP — ADSP and CDSP firmware.
Cellular modem (MPSS) — real, complete code, dormant for lack of a cellular front end (distinct from the unpopulated RF assets) — ADSP and CDSP firmware.
7.6.6. Provenance¶
- Source:
artifacts/boot_a/board.dts(cameraqcom,cam-*/qcom,cci/qcom,csiphynodes, absence of PCIe controller nodes,pcie_tbustub, HDMI DAIs / DBA codec,dp_display@ae90000),artifacts/dtbo_a/overlay_0.dts(declaredcam-sensor/eeprom/actuatormodules),_READONLY/lun1/xbl_a.bin(uefiplat.cfg## PCIE ##commentedPCIeRPNumber,TITAN_*MMAP windows).- Method:
DTB node census + presence/absence check + XBL config carve. No code executed.
- Cross-refs:
Pin control — TLMM and the PMIC GPIOs (CCI/MCLK pins, PM8008), Clock tree — GCC, domain CCs, RPMh (CAMCC), Base kernel device tree (the SoC boot contract) (pcie_tbu SMMU stub), Display pipeline — DSI transport to the color e-ink TCON (the real display path), ADSP and CDSP firmware (RF/HDMI-audio leftovers), Boot image: kernel, DTB, ramdisk, config (AMOLED reference leftover).